The present invention is directed to integrated circuits and their processing for the manufacture of semiconductor devices. More particularly, the invention provides a method and device for manufacturing a metal inter-connect structure exhibiting reduced defects. Merely by way of example, the invention has been applied to a copper metal damascene structure such as a dual damascene structure for advanced signal processing devices. But it would be recognized that the invention has a much broader range of applicability. For example, the invention can be applied to microprocessor devices, memory devices, application specific integrated circuit devices, as well as various other interconnect structures.
Integrated circuits or “ICs” have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Current ICs provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of ICs. Semiconductor devices are now being fabricated with features less than a quarter of a micron across.
Increasing circuit density has not only improved the complexity and performance of ICs but has also provided lower cost parts to the consumer. An IC fabrication facility can cost hundreds of millions, or even billions, of dollars. Each fabrication facility will have a certain throughput of wafers, and each wafer will have a certain number of ICs on it. Therefore, by making the individual devices of an IC smaller, more devices may be fabricated on each wafer, thus increasing the output of the fabrication facility. Making devices smaller is very challenging, as each process used in IC fabrication has a limit. That is to say, a given process typically only works down to a certain feature size, and then either the process or the device layout needs to be changed. An example of such a limit is the ability to form safe oxide layers of a predetermined thickness for MOSFET transistor structures.
FIG. 1A shows a simplified plan view of a conventional MOSFET transistor device. FIG. 1B shows a simplified cross-sectional view of the conventional MOSFET device of FIG. 1A.
Conventional MOSFET transistor 100 includes gate 102 comprising conducting polysilicon 104 overlying thin gate dielectric 106. Gate 102 is surrounded by shallow trench isolation (STI) structure 108.
Gate polysilicon 104 and peripheral portions 110a of the substrate 110 are in electrical communication with overlying metallization 112 through via contacts 114. The substrate 110 is also in electrical communication with metallization 112 through contact 116.
FIG. 1B is simplified in that gate drive 106 is typically very thin relative to the overlying gate polysilicon 104. During the course of operation of MOSFET device 100, the application of potential differences between gate contact 114 and substrate contact 116 imposes stress on the thin gate dielectric 106.
Accordingly, one important mechanism of breakdown of the MOSFET device is the unwanted surge of current from gate polysilicon 104 across the thin gate dielectric 106 into the substrate. The voltage at which this failure occurs is known as the breakdown voltage (Vbd). The mechanism by which this failure occurs over time is known as Time Dependent Dielectric Breakdown (TDDB).
During fabrication of the chip, Vbd and TDDB are not typically measured utilizing active portions of the integrated circuit. Instead, a test structure having no active functionality is intentionally created on the chip. Voltages are then applied to the test structure to determine Vbd and TDDB.
FIG. 2 shows a simplified plan view of a conventional test structure 200 for Vbd and TDDB. Active area 201 in the substrate 203 is surrounded by STI 202. Trace 204 is in electrical communication with the underlying substrate 203 through contact with window 206, and with edge polysilicon pad 208. Trace 210 is in electrical communication with the gate polysilicon, and in electrical communication with edge polysilicon pad 212. Application of a potential difference between edge polysilicon pads 208 and 212 would allow for testing of Vbd and TDDB based upon the character of the patterned gate dielectric and overlying polysilicon gate.
While the conventional test structure shown in FIG. 2 is effective to show breakdown of the gate oxide, it is not able to provide information regarding actual location of the breakdown event. Moreover, the conventional test structure is limited to testing the Vbd and TDDB properties just discussed.
From the above, it is seen that improved techniques and structures for testing semiconductor devices is desired.